A flat panel display device, as a mainstream display device at present, is widely used in electronic products such as a computer screen, a mobile phone, etc., due to its characteristics of slim shape, power conservation, no radiation, etc.
A display panel is a main component of the flat panel display device. As shown in FIG. 1, the display panel comprises a pixel region 1, a fan-out region 2 and a driving circuit region 3. The pixel region 1 comprises a plurality of gate lines 11 and a plurality of data lines 12 provided to intersect each other, a first insulation layer 13 (generally, a gate insulation layer) is provided between the gate line 11 and the data line 12, a second insulation layer 14 (generally, a passivation layer) is provided on the data line 12, and the gate line 11 and the data line 12 extend into the fan-out region 2, respectively. The driving circuit region 3 comprises gate driving chips for supplying gate scanning signals to the gate lines 11, and source driving chips for supplying data voltage signals to the data lines 12. As shown in FIGS. 2 and 3, a first via hole 15 penetrating through the first insulation layer 13 and the second insulation layer 14 is formed on the gate line 11 in the fan-out region 2, and a second via hole 16 penetrating through the second insulation layer 14 is formed on the data line 12 in the fan-out region 2, so that the gate driving chip is electrically connected with the gate line 11 through the first via hole 15, and the source driving chip is electrically connected with the data line 12 through the second via hole 16. The first via hole 15 and the second via hole 16 are generally formed by one patterning process, thereby reducing processing steps and saving costs.
The inventor found at least the following problem existing in the prior art. Since the first via hole 15 and the second via hole 16 are formed by one patterning process, the time spent in forming these two kinds of via holes by etching is the same. However, both of the first insulation layer 13 and the second insulation layer 14 are required to be etched when forming the first via hole 15, while only the second insulation layer 14 is required to be etched when forming the second via hole 16. Therefore, under the condition of the same etching time, an opening size of the second via hole 16 formed by etching is inevitably larger than that of the first via hole 15 formed by etching. In a case where pins of the gate driving chip are just completely inserted into the first via holes 15, i.e., the pins of the gate driving chip are completely wrapped by walls of the first via hole 15, since the opening size of the second via hole 16 is relatively large, it cannot be guaranteed that the pins of the source driving chip are completely wrapped by walls of the second via hole 16 when inserting the pins of the source driving chip into the second via holes 16, and consequently, the data line 12 below the second via hole 16 is exposed to be contaminated by external environment (water vapor, oxygen, etc.), thereby causing a connection failure and affecting a display effect.